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--- project:ledum:start [2025/04/25 13:13] – [Streaming Setup in Brmlab] joe
+++ project:ledum:start [2025/07/18 09:46] (current) – [Inctructions and assembly] sachy
@@ Line 116: / Line 116: @@
    * upto 64 PTR (Pointer registers)
    * special registers (CS:IP and several configuration registers probably)
-   *- No flag register (flags are going either to another GPR or to a special 4-bits adjacent to every GPR), this should help future with parallelization
+   * No flag register (flags are going either to another GPR or to a special 4-bits adjacent to every GPR), this should help future with parallelization
 === Pointers ===
@@ Line 125: / Line 125: @@
    * All RAM and registers is tagged, so ALU knows which type it's operating on and pointer cannot be created freely
    * Types: int, uint, float in 4, 8 ... 64 bit lengths fit in vector 64-bit long; Fat pointer, Ultra fat pointer
+=== SW-implemented services ===
+   * scheduler
+   * memory allocator
+   * IO allocator
+   * message broker
+   * garbage collector
+   * process creator
+Notes:
+# Any fiber can provide those services to others using it's resources. But the initial providers have all available resources and ability ru run privileged instructions if it's needed for their jobs.
+# Process hierarchy, memory quota hierarchy and IO hierarchy are completely independent.
+Terminology
+   * thread - X has asked scheduler to create it. X is it's parent and can see it's whole memory.
+   * process - X has asked process creator to create it. Process creator is it' parent and can see it's whole memory. X is it's parent process in process creator's data structures only. X doesn't have access to it's memory. It has nothing to do with IO or memory quotas, they can be set with different granularity.
+   * fiber - any thread or process
+   * There may be more process creators. Therefore the same fiber may be viewed as thread (from it's process creator and it's parent threads) and as process (from another process under the same process creator).
+   * Channel - some way of communicate which is using a tagged handle normal fiber can't create from integer (similar restriction like a FP has)
+== scheduler ==
+   * has HW capability to change settings of the HW scheduler in the CPU
+   * shouldn't be GCed probably (although it's data structures may utilize weak pointers)
+   * works on fibers (doesn't distinguish between process and thread)
+   * must know CS:IP and time-quota of every fiber
+   * contains fiber hierarchy
+   * fiber can push to it (via message containing FP) what childs it wants and how to divide it's time between them. Those information must be converted to absolute values by the scheduler, therefore they can't be used directly from fiber's memory, because that would trigger descent through tree and recalculation for every rescheduling.
+== memory allocator ==
+   * starts with FP to almost all memory (except memory given to other SW services)
+   * has information about what memory is empty and used
+   * has information about memory quotas
+   * when asked through some channel if can either allocate memory and return a FP or "create"#1 a new channel with some part of quota of the calling channel and return the new channel. It can shuffle the quota between already created channels to.
+   * it manages similar hierarchic structure as scheduler or process creator, but there are channels and their associated quotas in the tree
+#1 message handler will do the creation itself, but the channel will be between allocator and anyone who has the complementary handler given to the original caller
+== IO allocator ==
+   * it has capabilities to communicate with the IO somehow (via messages and DMA to FP?)
+   * it has information about which channel has rights to use what part of IO space
+   * any channel owner can ask for creating another channel with less rights -> therefore the structure is hierarchic
+   * any channel owner can ask for destruction of channel under it in the hierarchy
+   * any channel owner can ask it to do some IO and if it has enough rights, that IO will be done
+   * there may be more fibers behaving as IO allocator - it enables virtualization (lower allocator asks the higher one) and having non-HW IO capabilities (like to send a piece of memory to IP:port via TCP or UDP)
+== message broker ==
+   * creates channels and tags their handles. It may create 4 handles at once differing in the lowest 2 bits. Each pair of them is for one way of communication. The lowest bit may specify if the handle is sender or reciever. These handles are tagged, therefore no one else can create them.
+   * destroys channels after being asked to do so.
+   * it operates the mesasging HW.
+   * TODO: specify how the hw and messages itself will work
+   * TODO: How to ask a message broker for new handles with no handles? Handle 0 may be for communincation with mesage broker and working even without the proper tag? Another instruction?
+== garbage collector ==
+   * collect unused memory
+   * ignores the FP to the whole RAM in memory allocator
+   * collects unused handles to communincation channels too (TODO: somehow)
+Weak pointers will be needed probably.
+== process creator ==
+   * from the scheduler's point of view it is parent of all processes (fibers) running under it
+   * creates and destroys a processes when asked
+   * creates channels between parent and child process
+   * stores process hierarchy similarly as scheduler stores fiber hierarchy and memory allocator stores quota hierarchy
+There may be more process creators.
+The main reason for existence of process creator is possibility to create a child without being able to travel down through it's memory. Process creator will have this ability of course, but it should be small, simple and well audited.
+==== Inctructions and assembly ====
+  * Fixed-length instructions (64 bit) - decoder simplicity
+  * Instructions aligned to 64 bit addresses - decoder simplicity
+  * First 8 b is an opcode
+  * Macro-instructions (???)
+    * Single instruction is unrolled into multiple instuctions by instruction decoder and then executed by the CPU as if coded by hand
+    * Increased code density - things like clearing multiple registers by single "XRM 1,15" (Xor Register - Multiple reg_n,reg_m) unrolls into sequence XR 1,1,1 XR 2,2,2 ... XR 15,15,15 (Xor Register reg_result,reg_i,reg_j)
+    * Hardcoded in CPU wiring
+  * Supervisor Call Instructions
+    * Instruction passed outside of fiber/CPU and result passed back into specified register
+    * Raw-content register communication only, no way to pass memory
+    * Things like:
+      * Get current timestamp from BIOS or whomever
+      * Power management - tell the motherboard to sleep/turn off
+      * lowlevel ioctl used by hardware broker task
+      * VM communication?
+      * Allow itself being debugged?
+      * Message passing between fibers and basic services
+      * Inter-CPU communication (multicore, multisocket)
+  * Supported instruction set
+    * Derived from real-life massive applications by statistical analysis of used instructions
+    * Go along Parret rule that 20 % instructions do 80 % work - optimize that, ignore specialties
+    * Semaphores instructions
+      * Compare-swap
+      * ST0 - Store 0 or set condition code; ST1 - Store 1 or set condition code - if the memory was already non-zero (non-one), soft fail - atomic locking
+    * Vector processing
+      * Register treated as a vector of 4/8/16/32b long values
+    * Constant-time processing
+      * Compare-sort - order 4 registers by value in HW
+      * Hashing primitives
+      * Encrypt/decrypt primitives
+  * Inctruction naming convention to be defined
+  * Hex representation and opcode allocation to be defined
+  * Unused opcodes for future use
 ==== Electronic Circuit Design ====
@@ Line 151: / Line 255: @@
 As a proof-of-concept an assembly language compiler and IDE support was implemented for a very simple Harvard architecture 8-bit CPU. A graphical emulator for the same simple CPU was created as well. The aim of these tooling efforts is to provide a unified framework for creating custom instruction sets including their assemblers and emulators.
+<WRAP clear></WRAP>
+==== Simulator GUI ====
+{{ :project:ledum:qasireu-lqabec-socm1-gesicht.png?400|}}
+A simple GUI was developed for simulating a SOC written in Verilog.
 <WRAP clear></WRAP>